--VHDL instantiation template

component ecp5_ip is
    port (ip_gddr71rx_clk_phase: out std_logic_vector(6 downto 0);
        ip_gddr71rx_datain: in std_logic_vector(3 downto 0);
        ip_gddr71rx_q0: out std_logic_vector(6 downto 0);
        ip_gddr71rx_q1: out std_logic_vector(6 downto 0);
        ip_gddr71rx_q2: out std_logic_vector(6 downto 0);
        ip_gddr71rx_q3: out std_logic_vector(6 downto 0);
        ip_gddr71tx_data0: in std_logic_vector(6 downto 0);
        ip_gddr71tx_data1: in std_logic_vector(6 downto 0);
        ip_gddr71tx_data2: in std_logic_vector(6 downto 0);
        ip_gddr71tx_data3: in std_logic_vector(6 downto 0);
        ip_gddr71tx_dout: out std_logic_vector(3 downto 0);
        ip_gddr71rx_alignwd: in std_logic;
        ip_gddr71rx_clkin: in std_logic;
        ip_gddr71rx_phasedir: in std_logic;
        ip_gddr71rx_phaseloadreg: in std_logic;
        ip_gddr71rx_phasestep: in std_logic;
        ip_gddr71rx_pll_reset: in std_logic;
        ip_gddr71rx_ready: out std_logic;
        ip_gddr71rx_sclk: out std_logic;
        ip_gddr71rx_sync_clk: in std_logic;
        ip_gddr71rx_sync_reset: in std_logic;
        ip_gddr71tx_clkout: out std_logic;
        ip_gddr71tx_ready: out std_logic;
        ip_gddr71tx_refclk: in std_logic;
        ip_gddr71tx_sclk: out std_logic;
        ip_gddr71tx_start: in std_logic;
        ip_gddr71tx_sync_clk: in std_logic;
        ip_gddr71tx_sync_reset: in std_logic
    );
    
end component ecp5_ip; -- sbp_module=true 
_inst: ecp5_ip port map (ip_gddr71tx_data0 => __,ip_gddr71tx_data1 => __,ip_gddr71tx_data2 => __,
            ip_gddr71tx_data3 => __,ip_gddr71tx_dout => __,ip_gddr71tx_clkout => __,
            ip_gddr71tx_ready => __,ip_gddr71tx_refclk => __,ip_gddr71tx_sclk => __,
            ip_gddr71tx_start => __,ip_gddr71tx_sync_clk => __,ip_gddr71tx_sync_reset => __,
            ip_gddr71rx_clk_phase => __,ip_gddr71rx_datain => __,ip_gddr71rx_q0 => __,
            ip_gddr71rx_q1 => __,ip_gddr71rx_q2 => __,ip_gddr71rx_q3 => __,
            ip_gddr71rx_alignwd => __,ip_gddr71rx_clkin => __,ip_gddr71rx_phasedir => __,
            ip_gddr71rx_phaseloadreg => __,ip_gddr71rx_phasestep => __,ip_gddr71rx_pll_reset => __,
            ip_gddr71rx_ready => __,ip_gddr71rx_sclk => __,ip_gddr71rx_sync_clk => __,
            ip_gddr71rx_sync_reset => __);
